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Multi-lag cross-correlations (X-Corr) are essential building blocks in radar and communication for range/velocity detection and synchronization. Performing X-corrs necessitates efficient delay and correlation blocks. Traditionally, high bandwidth X-corr is performed using high-speed ADCs followed by digital multiply-and-accumulates (MACs). However, 5–20 TOPS/W X-Corr efficiencies lead to 0.1-1W per cross-correlator, limiting deployability in power-constrained applications. Alternatively, to realize X-corr using prior single-lag analog correlators, wideband analog delays (>10ns delays with 4GHz BW) should be integrated on chip to enable multiple lags. Furthermore, replicating N analog correlators, leads to an impractical chip area. Therefore, practical analog X-Corr requires: (i) high input bandwidths, (ii) long correlation length, N for high signal processing gain (SPG=10log10(N)), (iii) high compute-efficiency (>100 TOPS/W) with compute accuracy compared to digital MACs (>7-bit), (iv) single-shot readout across all N X-corr lags in a compact area. In this work, we leverage a sampling-based approach to create large analog delays and area/power-efficient four-transistor analog compute cell to present a margin-propagation (MP) based fully-analog X-Corr compute engine in 22nm SOI-CMOS achieving: (i) 1-4GS/s input, (ii) single-shot 256-length X-Corrs across all 256 lags resulting in a 256x256 X-correlator, 8.2-8.5 bit compute accuracy or hardware dynamic range (HDR) of 51-53dB, (iii) high compute efficiency of 996–1060 TOPS/W (6.6x better than SoA), (iv) high compute density of 1.3 TOPS/mm2 (7x better than SoA). We also demonstrate an X-band code-domain radar with a range resolution of 15cm across 256 range bins, supporting up to 1024 chirp averages with a 115Hz refresh rate. 

Introduction Securing wireless communications in internet-of-things (IoT) requires both generation and synchronization of random numbers in real-time. However, resource constraints on an IoT device limit the use of computationally intensive random number generators and the use of global positioning systems (GPS) for synchronization. In this paper, we propose a synchronized pseudo-random number generator (SPRNG) that uses a combination of a fast, low-complexity linear-feedback-shift-register (LFSR) based PRNG and a slow but secure, synchronized seed generator based on self-powered timers. Methods A prototype synchronized self-powered timer (SSPT) array was fabricated in a standard silicon process and was used to generate dynamic random seeds for the LFSR. The SSPTs use quantum-mechanical tunneling of electrons to operate without any external power and are practically secure against tampering, snooping, and side-channel attacks (both power and electromagnetic). Results In this work, we explore protocols to periodically and securely generate random bits using the self-powered timers for seeding the LFSR. We also show that the time-varying random seeds extend and break the LFSR periodic cycles, thus making it difficult for an attacker to predict the random output or the random seed. Using the National Institute of Standards and Technology (NIST) test suite we verify the randomness of the measured seeds from the fabricated ensemble of SSPTs together with the random bit sequences generated by a software-seeded LFSR. Discussions In this modality, the proposed SPRNG could be used as a trusted platform module (TPM) on IoTs and used for verifying and authenticating secure transactions (e.g., software upgrades). Since the SPRNG system does not require access to GPS for synchronization, therefore it could be used in many resource-constrained and adversarial environments. 

Introduction For artificial synapses whose strengths are assumed to be bounded and can only be updated with finite precision, achieving optimal memory consolidation using primitives from classical physics leads to synaptic models that are too complex to be scaled in-silico . Here we report that a relatively simple differential device that operates using the physics of Fowler-Nordheim (FN) quantum-mechanical tunneling can achieve tunable memory consolidation characteristics with different plasticity-stability trade-offs. Methods A prototype FN-synapse array was fabricated in a standard silicon process and was used to verify the optimal memory consolidation characteristics and used for estimating the parameters of an FN-synapse analytical model. The analytical model was then used for large-scale memory consolidation and continual learning experiments. Results We show that compared to other physical implementations of synapses for memory consolidation, the operation of the FN-synapse is near-optimal in terms of the synaptic lifetime and the consolidation properties. We also demonstrate that a network comprising FN-synapses outperforms a comparable elastic weight consolidation (EWC) network for some benchmark continual learning tasks. Discussions With an energy footprint of femtojoules per synaptic update, we believe that the proposed FN-synapse provides an ultra-energy-efficient approach for implementing both synaptic memory consolidation and continual learning on a physical device. 

Growth-transform (GT) neurons and their population models allow for independent control over the spiking statistics and the transient population dynamics while optimizing a physically plausible distributed energy functional involving continuous-valued neural variables. In this paper we describe a backpropagation-less learning approach to train a network of spiking GT neurons by enforcing sparsity constraints on the overall network spiking activity. The key features of the model and the proposed learning framework are: (a) spike responses are generated as a result of constraint violation and hence can be viewed as Lagrangian parameters; (b) the optimal parameters for a given task can be learned using neurally relevant local learning rules and in an online manner; (c) the network optimizes itself to encode the solution with as few spikes as possible (sparsity); (d) the network optimizes itself to operate at a solution with the maximum dynamic range and away from saturation; and (e) the framework is flexible enough to incorporate additional structural and connectivity constraints on the network. As a result, the proposed formulation is attractive for designing neuromorphic tinyML systems that are constrained in energy, resources, and network structure. In this paper, we show how the approach could be used for unsupervised and supervised learning such that minimizing a training error is equivalent to minimizing the overall spiking activity across the network. We then build on this framework to implement three different multi-layer spiking network architectures with progressively increasing flexibility in training and consequently, sparsity. We demonstrate the applicability of the proposed algorithm for resource-efficient learning using a publicly available machine olfaction dataset with unique challenges like sensor drift and a wide range of stimulus concentrations. In all of these case studies we show that a GT network trained using the proposed learning approach is able to minimize the network-level spiking activity while producing classification accuracy that are comparable to standard approaches on the same dataset.